# Multi-Core Architecture Support

> **The criterion.** Does the RTOS support SMP (one kernel balancing threads across identical cores) and/or
> AMP (separate kernel instances per core, communicating via shared memory), and can it pin critical threads
> to designated cores?

## How Revera answers it

Revera does **both, on one portable core**. In **SMP** a single kernel schedules across several cores from a
shared ready set. In **AMP** an application declares independent kernel **islands**, each owning a disjoint
set of cores — and (the differentiator) those islands can be made hardware-isolated so one cannot reach
another's memory (see [Memory Protection & Isolation](memory-protection-isolation.md)). A heterogeneous mix
is supported: one SMP island beside a separate single-core island, as proven on AURIX TriCore.

## Feature · how to turn it on · how to use it · where it works

| Feature | Turn on with | Use these APIs | Where |
|---|---|---|---|
| SMP (one kernel, N cores) | `SMP=<n>` (board knob → `TK_SMP_CORES`) | (automatic scheduling) | RP2040 (Cortex-M0+), Cortex-A, RISC-V, AURIX |
| AMP islands (multi-instance) | `tk_kernel_define(...)` | `tk_kernel_define` / `set_ram` / `self` / `default` / `find` / `count` / `at` | same set |
| Core affinity / pinning | `TK_CONFIG_ENABLE_AFFINITY` | `tk_thread_set_affinity`, `tk_thread_pin` | SMP builds |
| Cross-core synchronization | — | `tk_spin_*` (spinlock), `tk_seq_*` (seqlock) | SMP builds |
| Cross-island memory fence | `TK_CONFIG_ENABLE_INSTANCE_ISOLATION` | `tk_kernel_define` / `set_ram` / `set_trusted` | see the isolation axis |
| Cross-island liveness | — | `tk_kernel_liveness_check`, `tk_kernel_on_stall` (weak hook) | all |

*Full signatures and contracts: [API reference — Kernel lifecycle & instances / Synchronization](../reference/api.md).*

## Limits & roadmap

- SMP core count is a board property (`make -C <example> boards`); a build asking for more cores than the
  board has fails loud.
- The cross-island fence's arch coverage is the isolation axis's — not every multi-core target is
  fence-capable.

## Learn more

- **How it works:** [SMP model](../architecture/smp-model.md) · [ADR 0002 — multi-instance kernel](../decisions/0002-multi-instance-kernel.md).
- **Run it:** `examples/threads_smp` (SMP) · `examples/amp_islands` / `amp_spawn` / `amp_sync` (AMP) ·
  `examples/amp_kernel_fence` (isolated islands).
- **Full API:** [API reference](../reference/api.md).