0.1.0 Readiness Dashboard — LIVE

This is a living document. Update statuses in place as work lands — do not append a new copy. Full evidence for every row is in status-1.md. Last updated 2026-09-03. North-star goal: ship a named, self-contained 0.1.0 dev release of the portable RTOS microkernel with commercial-grade attributes (versioning, license, docs, tested, honestly-scoped roadmap).

How to read this

Each capability carries a maturity status, the user-facing API state (does the user call it today or is it coming), and per-architecture support. The API column separates the user-level perspective (“what can I call?”) from the implementation scope (“where does it actually run?”).

Maturity legend

	Meaning
✅ Completed	Implemented and HW-verified on silicon
🟢 Implemented	In root tree; builds + runs (QEMU/host), not yet HW-verified on that target
🟡 Partial	Present as a stub, one half, or a renamed subset — not the full capability
⚪ Planned	Not in root; proven in _legacy/ and/or on the roadmap
➖ N/A	Architecture cannot support this (no HW mechanism)
—	Not yet assessed on this target

API-state legend — E = Existing API (public in root headers today; 0.1.0 freeze candidate) · E~ = existing but internal/unstable (not freeze-ready) · P = Planned API (to be introduced) · P~ = planned, API shape not yet designed.

Architecture columns — H Host (pthread/flat) · M ARM-M (v6/7/8-M) · A/R ARM-A/R (v7a/v8a/v8r) · RV RISC-V rv32 · TC TriCore (AURIX) · C2 C2000 (C28x) · 430 MSP430. Legacy-only arches AVR and Xtensa/ESP32 are tracked in § Target breadth (Tier 4), not in every grid.

⚠️ Statuses are best-known as of the date above; correct them in place when a build/run says otherwise.

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Release scorecard (0.1.0)

Tier	Theme	State	Blocking 0.1.0?
Asset	Differentiated kernel core (sched/sync/isolation/SMP/AMP)	✅ proven	—
0	Productization (versioning, license, docs, test harness)	🟢 done — all core artifacts ✅; only 🟡 dedicated limitations/coding-guidelines docs + deferred competitive one-pager remain	YES — primary work
1	Finish stubbed core (canary, introspect, board-wiring, hygiene)	🟢 honesty gaps closed (canary + profiling getters + introspect doc + isolation fail-loud gate + hygiene)	done
2	HAL / driver breadth	⚪ planned	No — roadmap
3	Security / safety planes	⚪ planned (HW-proven in _legacy)	No — roadmap
4	Target breadth (extra arches/boards)	🟡 partial	No — pull-driven

0.1.0 = Asset (done) + Tier 0 + Tier 1. Tiers 2–4 ship as a documented, honest roadmap.

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1 · Kernel & scheduling

Capability	API	H	M	A/R	RV	TC	C2	430	Notes
Threads (create/exit/join)	E	🟢	✅	🟢	🟢	✅	✅	⚪	tk_thread_*; 430 kernel port unproven (boards HAL-only)
Preemptive scheduler	E	➖	✅	🟢	🟢	✅	✅	⚪	host is cooperative (pthread)
Priorities	E	🟢	✅	🟢	🟢	✅	✅	⚪	TK_PRIO_MIN..MAX
EDF / deadlines	E	🟢	🟢	🟢	🟢	🟢	🟢	⚪	TK_CONFIG_ENABLE_EDF (default off), tk_thread_set_deadline
Time / tick / sleep	E	🟢	✅	🟢	🟢	✅	✅	⚪	per-instance time_base; tk_time_us is ms×1000 (sub-tick = P)
Idle / low-power (arch_idle)	E~	➖	✅	🟢	🟢	✅	✅	⚪	WFI/WAITI/SLEEP; no tickless framework

2 · Synchronization

Capability	API	H	M	A/R	RV	TC	C2	430	Notes
Mutex + priority inheritance	E	🟢	✅	🟢	🟢	✅	✅	⚪	single-level PI (tk_sync.c)
Semaphore	E	🟢	✅	🟢	🟢	✅	✅	⚪
Condition variables	E	🟢	✅	🟢	🟢	🟢	🟢	⚪	pthread-shaped; no dedicated demo at root
Join / detach / attrs	E	🟢	✅	🟢	🟢	✅	✅	⚪
Spinlock / seqlock (SMP)	E	➖	🟢	🟢	🟢	✅	➖	➖	tk_spinlock.h/tk_seqlock.h; TC HW-verified

3 · Isolation & multicore ⭐ the differentiator

Capability	API	H	M	A/R	RV	TC	C2	430	Notes
MPU stack-guard (overflow)	E	➖	✅	🟢	🟢	✅	➖	➖	region + paging archs; C2000/430 incapable
Unprivileged threads	E	➖	✅	🟢	🟢	✅	➖	➖	M: RA4M1 + M33 HW; TC: unpriv_tricore HW
Per-thread stack isolation	E	➖	✅	🟢	🟢	✅	➖	➖	full-lockdown
Supervisor fence (AMP island)	E	➖	✅	🟢	🟢	✅	➖	➖	USP; TC HW-verified 2026-09-02 (amp_kernel_fence_tricore)
World / TrustZone-AMP (S/NS)	E	➖	✅	➖	➖	➖	➖	➖	ARM v8-M; MCXN947 HW (ADR 0005)
SW stack canary (L1)	E	✅	🟢	🟢	✅	🟢	🟢	🟢	tk_stack.c real (fill + canary/switch + hook); host unit-tested + RV live-verified; direction-aware (grows-up TC/C2)
SMP (single kernel, N cores)	E	➖	✅	🟢	🟢	✅	➖	➖	M: RP2040 HW; TC: 3-core HW
AMP islands (multi-instance)	E	🟢	✅	🟢	🟢	✅	➖	➖	tk_kernel_define
Cross-core wake / IPI	E	➖	✅	🟢	🟢	✅	➖	➖
Cross-core reclaim (slots/CSA)	E	➖	🟢	🟢	🟢	✅	➖	➖	TC CSA reclaim-to-home HW (csa_reclaim_smp_tricore)

Fence mechanism coverage (USP): 5 mechanisms / 2 classes — region-MPU (ARM v8-M ✅HW, v7-M ✅HW, R52 🟢QEMU) + paging (RISC-V Sv32 🟢QEMU, ARM VMSA 🟢QEMU) + TriCore PRS/DPR (✅HW) + system-side AHBSC/TrustZone (MCXN947 ✅HW, ADR 0005).

4 · Observability & fault

Capability	API	H	M	A/R	RV	TC	C2	430	Notes
Trace ring (flight recorder)	E	🟢	✅	🟢	🟢	🟢	🟢	—	tk_trace_ring.c
SEGGER SysView	E	➖	✅	—	—	—	—	—	nRF52 HW
Panic / post-mortem / hardfault	E	🟢	✅	🟢	🟢	🟢	🟢	—	panic, hardfault
Stack high-water	E	✅	🟢	🟢	🟢	🟢	🟢	🟢	tk_thread_stack_peak / _free; host unit-tested
Thread snapshot	E	🟢	✅	🟢	🟢	✅	🟢	—	tk_kernel_thread_snapshot
Remote monitor (ps/top region)	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	ENABLE_INTROSPECT = thread NAMES (doc fixed); external RAM-window monitor still roadmap
Runtime stats accessor	E	✅	🟢	🟢	🟢	🟢	🟢	🟢	tk_thread_cpu_ticks / _run_count (under TK_CONFIG_ENABLE_PROFILING)
Fault containment	E	➖	✅	🟢	🟢	✅	—	—	TK_CONFIG_FAULT_CONTAIN
Liveness / stall detect (island)	E	🟢	✅	🟢	🟢	✅	—	—	tk_kernel_liveness_check

5 · Safety (Tier 3 — mostly planned; HW-proven in _legacy)

Capability	API	H	M	A/R	RV	TC	C2	430	Notes
Watchdog kick seam (kernel)	E	🟢	✅	—	—	—	—	—	tk_watchdog_kick; watchdog nRF52 HW
Watchdog (portable MCAL)	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	legacy tk_wdg (nRF52/ESP32/host)
Reset-reason	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	legacy tk_mcu_reset_reason (5 SoCs)
Brownout detect	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	legacy nRF52/STM32 HW
Persistence (validated)	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	legacy tk_persist (magic+CRC+len)
.noinit RAM (raw)	E	🟢	🟢	—	—	—	—	—	noinit (no integrity gate)
Cross-core heartbeat	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	legacy tk_heartbeat per-core
Error / DET reporting	P~	🟡	🟡	🟡	🟡	🟡	🟡	🟡	root tk_det.h = no-op stub; legacy full subsystem
Functional-safety lifecycle	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	legacy docs/k2/ ISO-26262-style tree

6 · Security / crypto / boot (Tier 3 — planned; HW-proven nRF52 in _legacy)

Capability	API	H	M	A/R	RV	TC	C2	430	Notes
SHA-256 / HMAC-SHA256	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	SW + ESP32 HW backend
AES-128 (ECB / CBC)	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	nRF52 ECB / ESP32 / host SW
ECDSA P-256 verify	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	from-scratch, verify-only
RNG / TRNG	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	nRF52/ESP32 HW; host PRNG
CRC-16	P	⚪	⚪	⚪	⚪	⚪	⚪	⚪	SW default + MSP430FR HW
Verified boot (HMAC/ECDSA/2-stage)	P	⚪	⚪	—	—	—	—	—	tk_vboot; HW-verified nRF52
APPROTECT / debug lockout	P	➖	⚪	—	—	—	—	—	nRF52 HW-verified

7 · HAL peripherals (Tier 2 — contract-compatible re-attach; all planned at root)

Existing at root: DIO/GPIO (tk_port_* config + tk_dio_* operate), UART-TX, edge-IRQ (tk_dio_irq), clock (tk_mcu). Everything below is P (planned) — legacy backends noted.

Peripheral	API	Legacy backends (portability proof)	Root
GPIO / DIO (config + operate)	E	nRF52, RA4M1, STM32, RP2040, TC275, …	🟢
UART TX	E	all boards	🟢
UART RX (ring)	P	legacy tk_uart_rx.c	⚪
GPIO edge IRQ	E	nRF52 (tk_dio_irq)	🟢 (M)
GPIO zero-CPU routing (PPI)	—	nRF52 GPIOTE MODE B	➖ excluded from contract
Timer (GPT, app countdown)	P	nRF52, AVR, MSP430×2 + core (5)	⚪
ADC	P	nRF52, AVR, MSP430×2, host (5)	⚪
I2C (master + slave)	P	nRF52, AVR, MSP430×2, host (5)	⚪
SPI (master)	P	nRF52, AVR, MSP430, host (4)	⚪
PWM	P	nRF52, AVR, MSP430×2, host (5)	⚪
ICU (input capture)	P	nRF52, MSP430FR (2)	⚪
RTC (low-power)	P	nRF52, MSP430FR (2)	⚪
TEMP (die)	P	nRF52, host (2)	⚪
NFCT (tag) / BLE beacon	P~	nRF52 only	⚪ single-silicon

8 · Drivers & off-chip devices (Tier 2 — whole layers absent at root)

Item	API	Legacy	Root
Button (debounce + gestures)	P	drivers/tk_button	⚪
LED (logical)	P	drivers/tk_led	⚪
Persist driver	P	drivers/tk_persist	⚪
LCD HD44780 (GPIO / PCF8574)	P	devices/hd44780*	⚪
CAN MCP2515	P	devices/mcp2515	⚪
I2C expander PCF8574	P	devices/pcf8574	⚪
NFC PN532	P	devices/pn532	⚪

9 · Build, tooling & product infrastructure (Tier 0 — the ship wrapper)

Item	Status	Notes
Build system (make/tk.mk, per-example)	🟢	present
Profiles (nano/dev/full/hardened)	🟢	root is a superset of legacy
Config system (tk_config + TK_FEAT_*)	🟢	capability layer added in reshape
Arch/config regression checks (check_*.sh)	🟢	fence-matrix, arch-detect
Unit-test harness (host + QEMU)	⚪	legacy tests/ (tb_test, kernel/mutex/cond/handle/stack/crc/uart_rx + riscv arch) — not at root
Quality-gate Makefile (test/coverage/MC-DC/MISRA/check-profiles)	⚪	legacy top-level Makefile — not at root
Coverage / MC-DC / MISRA gates	⚪	gcov / LLVM MC-DC / cppcheck MISRA C:2012
tkgen pin/clock codegen	⚪	legacy tools/tkgen (YAML → const C)
Composability CI gate	⚪	legacy composability_matrix.sh (I1–I4)
Versioning (VERSION + gen_version.sh)	⚪	legacy 0.1.0-dev + build-stamp header
SDK packaging (tk_pkg.sh)	⚪	legacy self-describing SDK per board

Target breadth (Tier 4)

Target	Kind	Status	Notes
AVR (ATmega328P) arch + Uno board	arch+board	⚪	legacy, rich HAL
Xtensa LX6 (ESP32) arch + Wrover board	arch+board	⚪	legacy; SMP staged
MSP430FR2433 board	board	⚪	legacy; most complete peripheral set (HAL-only)
MSP430G2553 board	board	⚪	legacy; HAL-only superloop
RA4M1 (r7fa4m1ab_ek) board	board	⚪	legacy; full kernel-capable ARM
STM32F103 Blue Pill board	board	⚪	legacy; kernel-capable
STM32H723 Nucleo board	board	⚪	legacy; kernel-capable

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10 · Productization checklist (0.1.0 gate)

Artifact	Status	Notes
Product name	✅	Revera, by VIACERTO LLC
LICENSE + SPDX headers	✅	PolyForm Noncommercial 1.0.0 OR VIACERTO commercial; 226 files stamped
VERSION + SemVer scheme	✅	0.1.0
CHANGELOG.md (Keep-a-Changelog)	✅
Project README (pitch → USP → quickstart → support matrix → limitations)	✅
Getting-started guide	✅	docs/guides/getting-started.md (desktop → QEMU → own app)
User manual / API reference	🟢	docs/reference/api.md + docs/README.md (manual index)
Porting guide	🟢	docs/guides/{arch-porting,board-bringup}.md
Supported-target matrix (Tier-1/2/3)	🟢	this dashboard
Limitations & Non-Goals	🟡	in README status + CHANGELOG “Known limitations”; dedicated doc pending
Coding guidelines	🟡	in CONTRIBUTING (C99 -Werror -pedantic, style, tk_ prefix); dedicated doc pending
Release manifest / “what’s in the box”	✅	docs/release-manifest.md
CONTRIBUTING + feedback process	✅	CONTRIBUTING.md with the dual-license CLA
Competitive one-pager	🟡	docs/evaluation/ (13 axes) is the seed (deferred)
Announcement / release notes	✅	docs/announcements/0.1.0.md

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Update log

• 2026-09-03 — Dashboard created from Readiness Review #1 (status-1.md). Baseline statuses set.